FIG. 8 shows a process flow of a prior art fabricating method of a semiconductor device. FIG. 9 is a sectional view of an FET structure formed by the prior art method. In FIG. 9, reference numeral 1 designates a semi-insulating GaAs substrate having a thickness of about 600 .mu.m and an impurity concentration of 1.times.10.sup.15 cm.sup.-3. Reference numeral 2 designates an active layer having a thickness of about 0.5 to 0.6 .mu.m and an impurity concentration of 1 to 3.times.10.sup.17 cm.sup.-3. Reference numeral 3 designates an alloy base ohmic electrode comprising such as Au, Ge, or Ni and having a thickness of 0.3 to 0.4 .mu.m. Reference numeral 4 designates a gate electrode having Al as its main component and having a height of 0.45 to 0.6 .mu.m and a gate width of 0.5 to 1 .mu.m.
A description is given of the prior art process flow shown in FIG. 8.
Initially, a substrate including an epitaxial film grown to a prescribed standard is prepared (step S1), and ohmic electrodes 3 are formed (step S2). Then, a saturation current between the ohmic electrodes is adjusted by recess etching so that, for example, a thickness of an active layer is 0.15 .mu.m (1500 angstroms). Thereafter, a gate electrode is formed on the recess, whereby an FET including a recess gate having a sectional structure shown in FIG. 9 is formed (step S3). Further, other processes, such as formation of wiring and a passivation film, are performed (step S7), thereby completing the whole process flow of the prior art.
In the above-described prior art process flow, the FET characteristics are adjusted only when the recess gate is formed (step S3). However, because it is impossible to correct minute variations of such as 1.times.10.sup.16 cm.sup.-3, in the carrier concentration of the epitaxial film by an adjustment, respective devices have different yields and it is impossible to fabricate and provide a device with a stable yield.